Deposition and etch processes: continuum film evolution in microelectronics
Review articleOpen access

AbstractAspects of modeling and simulation of topography evolution during deposition and etch processes used in the fabrication of integrated circuits are discussed. Overall, we hope to demonstrate that combined simulation and experimental studies of film profiles and composition profiles inside features is a valuable tool in efforts to arrive at useful kinetic and transport models. In particular, conformality limitations and film composition variations inside features for films deposited at low pressures are explained using examples of studies that combine transport and reaction simulations of deposition processes and carefully designed experimental work. The technical presentation is divided into three major parts. In the first section, we demonstrate that thermal systems can be modeled without “calibrating” the transport and reaction models used, though calibration can still be useful. The process considered in this section is the thermal deposition of SiO2 from TEOS (tetraethoxysilane). We discuss the use of film profile information to decide between two kinetic models for the deposition process, then we discuss one way to integrate reactor scale and feature scale models in order to capture “microloading” due to changes in local pattern density. The second section demonstrates the state of topography simulation for plasma processes. We demonstrate the use of physically motivated models that in general require calibration from experimental data for a given set of operating conditions. As our first plasma example, we use the sputter deposition of Ti–W to demonstrate the existence of composition profiles inside features. We then use etch simulations to show how simulations can be used to test proposed chemical and/or physical phenomena. The last major section is a case study on plasma enhanced deposition of SiO2 from TEOS and oxygen (PETEOS) that demonstrates the roles of “3d/2d” and “3d/3d” (transport dimensionality/surface dimensionality) topography simulators in “virtual wafer fabs”. The same methodology would apply to most topography relevant processes, including thin film flow processes.

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