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An integrated DFT solution for power reduction in scan test applications by low power gating scan cell

Mahshid Mojtabavi Naeini - No affiliation found

2017/03/01 Full-length article DOI: 10.1016/j.vlsi.2016.12.009 Journal: Integration

Abstract:

Highlights•Integrated Low Power Gating Scan Cell is proposed to alleviate shift power.•Critical Path Integrated Gating Scan Cell is proposed to speed up launch operation.•An average power reduction of 15.12% for ILPG over conventional scan cell.•Up to 39.15% improvement compared to one of the most popular gating techniques.•Up to 51.42% reduction in CLK-to-shift delay over conventional scan is achieved.