An integrated DFT solution for power reduction in scan test applications by low power gating scan cell
Review articleOpen access
Abstract:

Highlights•Integrated Low Power Gating Scan Cell is proposed to alleviate shift power.•Critical Path Integrated Gating Scan Cell is proposed to speed up launch operation.•An average power reduction of 15.12% for ILPG over conventional scan cell.•Up to 39.15% improvement compared to one of the most popular gating techniques.•Up to 51.42% reduction in CLK-to-shift delay over conventional scan is achieved.

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