Leakage characterization of top select transistor for program disturbance optimization in 3D NAND flash
Review articleOpen access

Highlights•A characterization approach is proposed to quantify TSG leakage under program inhibit.•Optimization of program disturbance has been carried out with this approach.•An optimal TSG Vth pattern is suggested for low leakage and high boosting efficiency.•Upper TSG plays dominant role in preventing DIBL leakage in optimal TSG vth pattern.•Lower TSG assists to suppress trap assisted BTBT between dummy WL to edge of TSG.

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